Decoupled Vector Architectures: a Rst Look

The purpose of this paper is to show that using decoupling techniques in a vector processor, the performance of vector programs can be greatly improved. We will show how, even for an ideal memory system with no latency, decoupling provides a signiicant advantage over standard mode of operation. We will also present data showing that for more realistic latencies, decoupled vector architectures perform substantially better than non-decoupled vector architectures. We will also introduce a bypassing technique between the queues and show how it can reduce the total memory traac. A side eeect of the decoupling technique presented is that it tolerates so well long memory latencies that could make feasible to use very slow DRAM parts in vector computers in order to reduce cost.